test bus
英 [test bʌs]
美 [test bʌs]
网络 测试总线
双语例句
- Based on the research of boundary scan and cluster test, a cluster test system is designed with test Bus controller chip, then it is verified with the GNS algorithm of W-A.
在对边界扫描及簇测试技术研究的基础上，以边界扫描测试总线控制器芯片为核心设计实现了一个簇测试系统，选择W-A的GNS算法对所设计的测试系统进行了簇测试实例验证。 - Design and Test of CAN Bus Controller Based on Verilog HDL
基于Veriloghdl语言的CAN总线控制器设计及测试 - The Handling Stability and Ride Comfort Simulation and Test Research of Bus with Air Spring;
汽车平顺性仿真研究的关键在于仿真模型的建立和分析方法的确立。 - Twin oblique photograph tilting test [ double-decked bus]
双镜头倾斜航摄照片倾斜试验〔双层巴士〕 - Research on the Boundary-Scan Test Bus Fault Diagnosis and Its Strategy for VLSI
VLSI边界扫描测试故障诊断及其策略研究 - Application of test bus controller in the high-performance time measurement system
TBC控制器在高性能时间测量系统中的应用 - Research on simulation of dynamic overturn test for bus
客车动态翻滚试验仿真研究 - In the high-performance time measurement system, the high performance time-to-digital converter chip can only be initialized and controlled by JTAG. A test bus controller is used to realize functions of JTAG.
在高性能时间测量系统中，高性能时间数字转换芯片只能通过JTAG进行初始化和控制，为此选择了TBC控制器来实现的方法。 - The Module Test and Maintenance Bus Running Mechanism
模块测试与维护总线的工作机制 - On-load Test of Bus Differential Protection
母线差动保护带负荷测试 - In this paper, the DFT standards series based on standard test bus are analyzed, and the testability design methods of applying boundary scan technology in board level test, system level test and products field maintenance are put forward.
在分析基于标准测试总线的测试性技术的标准体系之后，介绍了将边界扫描技术应用于板级测试，系统级测试以及产品现场维护的测试性设计的一种方法。 - 1394 OHCI program realized the test of 1394 bus configuration, the status transfer of physical layer, the transmission and reception of 1394 asynchronous packets.
1394OHCI程序设计包括总线配置检测、物理层状态传送、异步数据包的发送和接收的实现。 - Module Test and Maintenance Bus
模块测试与维护总线 - In this paper, IEEE 1149.4 Std mixed-signal test bus and its characteristic are studied. According to the structure defined in this standard, test methods of mixed-signal circuits are studied. The mixed-signal boundary-scan test system, which is complianted to IEEE 1149.4 Std, is designed.
本文深入研究了IEEE1149.4混合信号测试总线及其特点，并根据边界扫描标准定义的测试结构对混合信号电路的测试方法进行研究，设计出符合IEEE1149.4标准的混合信号边界扫描测试系统。 - The IC chip structure that supports JTAG standard, 4-wire serial bus and fault diagnosis principles of the boundary scan test bus were introduced.
介绍了支持JTAG标准的IC芯片结构和故障测试的4-wire串行总线，以及运用边界扫描故障诊断的原理。 - Research of Wind Tunnel Test for a Bus Model
客车模型风洞试验研究 - In the experiments, the fault type of IC test bus, the fault diagnosis flow and the test principles were analyzed, and a fault diagno-sis strategy of test bus was proposed.
实验中分析了IC故障类型、一般故障诊断流程和进行扫描链本身完整性测试的方案，并提出了一种外加测试码向量生成的算法。 - The principle of test bus is analyzed and general chip test architecture based on test bus is presented in the dissertation.
本文详细分析了测试总线的原理，并给出基于测试总线的通用芯片测试结构。 - This architecture can test the data path of wrapper cells and resolve the problem of safe shifting of scan chains during shifting, also allows different cores to be connected directly to the same test bus.
实现了对内核测试壳单元的功能数据路径测试，并改善了内核测试壳单元扫描链安全移位，同时实现了允许共用同一条测试总线的不同IP核直接连接到测试总线上。 - In this paper the structure and feature of module test and maintenance bus are summarily described.
简要阐述了模块测试与维护总线的结构及特点； - The architecture allows different cores to be connected directly to the same test bus.
该结构允许共用同一条测试总线的不同IP核直接连接到测试总线上。 - The Development and Capability Comparing for the Test Bus
测试总线的发展及性能比较 - During test application test data is broadcasted to every core under test by bus, thereby implementing concurrent test of multiple cores.
测试应用时总线广播测试数据到各个被测芯核，从而实现多核的并行测试。 - This paper presents an automatic test scheme for mixed PCB, which is based on standard test bus ( VXI and GPIB).
提出了一种基于标准测试总线（VXI和GPIB）的混合电路板的自动测试方案。 - The Analysis on Electromagnetic Compatibility for VXI Test Bus System
VXI测试总线系统的电磁兼容分析 - The system examination platform to test bus switch property is built to prove the feasibility of using redundancy CAN bus.
然后，为了验证冗余CAN总线设计方案的可行性，搭建试验平台并进行CAN总线故障切换的试验； - A chip test architecture based on test bus is analyzed in the paper, and test scheduling in SOC is explained. Finally, the design of the chip test controller is presented, which is capable of carrying out test scheduling.
文章分析了基于测试总线的芯片测试结构，详细阐述了SOC设计中测试调度的概念，给出了一种能够灵活实现各种测试调度结果的芯片测试控制器的设计。 - Presents a functional test based universal bus emulation test system, and a detailed introduction of its hardware and software system is presented.
提出了一种基于功能测试的可编程通用总线仿真测试系统，并对其硬件和软件系统的组成原理和功能做了详细的介绍。